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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Angel College of Engineering and Technology, Tirupur-641665, IN
Source
International Journal of Scientific Engineering and Technology, Vol 3, No 3 (2014), Pagination: 276-279
Abstract
Error correction codes are commonly used to protect memories from soft errors, which change the logical value of memory cells without damaging the circuit. As technology scales, memory devices become larger and more powerful error correction codes are needed. Majority logic decoding is efficient technique due to their capability to correct multi number of errors, less time and area consumption. The proposed error-detection and correction is achieved by using 2D parity check, checksum, CRC methods with majority logic decoding. This proposed method is more efficient than the existing method as it reduces the memory access time when there is no error in the data read. This proposed technique is implemented by using Xilinx design suite 12.1.
Keywords
Low Density Parity Check, Different Set Codes, Error Correction Codes, Majority Logic Decoding.
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